Seeed Arch Link Board (VAR)

Arch Link is an mbed enabled development board based on Nordic nRF51822 and WIZnet W5500 ethernet interface. With Arduino form factor, Grove connectors and micro SD interface, it is extremely easy to create a bluetooth low energy device.

Features

  • mbed enabled
    • Online IDE
    • Easy to use C/C++ SDK
    • Handy libraries
  • CMSIS DAP based on LPC11U35
    • Drag-n-drop programming
    • Debug using CMSIS DAP standard
    • USB virtual serial for communication
  • Arduino form factor with Grove connectors
    • I2C and UART connecter on board
  • Nordic nRF51822 Multi-protocol Bluetooth® 4.0 low energy/2.4GHz RF SoC
    • ARM Cortex M0 processor
    • 256kB flash/16kB RAM
    • Configurable I/O mapping for digital I/O
  • WIZnet W5500 Ethernet
    • Supports following Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
    • Supports Power down mode
    • Supports Wake on LAN over UDP
    • Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
    • Internal 32Kbytes Memory for Tx/Rx Buffers
    • 10BaseT/100BaseTX Ethernet PHY embedded
    • with RJ45 connector
  • USB Micro B connector
  • Micro SD Card connector

https://developer.mbed.org/platforms/Seeed-Arch-Link/

WIZnet New Product “WIZwiki-W7500P”

WIZwiki-W7500

WIZwiki Platform

WIZnet WIZwiki Platform based on WIZnet’s MCU. WIZnet WIZwiki-W7500P is a WIZwiki platform board based on W7500P. The IOP4IoT W7500P chip is the one-chip solution which integrates an ARM Cortex-M0, 128KB Flash, hardwired TCP/IP core for various embedded application platform, 10/100 Ethernet MAC and PHY, and especially internet of things. The TCP/IP core is a market-proven hardwired TCP/IP stack and PHY is IC plus IP101G, an IEEE 802.3/802.3u Fast Ethernet Transcevier for 10/100Mbps. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for more than 15 years. W7500P suits users who need Internet connectivity best.

For more information, please visit: http://wizwiki.net/wiki/doku.php?id=products:wizwiki_w7500p:start.

To purchase this product, please visit: http://www.shopwiznet.com/wizwiki-w7500p.

[WIZnet’s New Product] WIZwiki-W7500ECONET

sub_banner_20151016_w7500econet_real

We are currently offering sales on our new product “WIZwiki-W7500ECONET” at a special rate just for our valuable customers. In stock and available now. No need to create an account to get this offer. Offer is only available at our online store; www.shopwiznet.com/wizwiki-w7500econet. Offer expires on December 31st 2015. The price applies to the purchase price (excluding shipping, handling, and taxes) of the products. First come, first served basis. The number of this product is limited.

 

WIZnet W7500 System and Memory Overview

We will learn about WIZnet W7500 system and memory in this chapter.

Specifically, We will learn about WIZnet W7500 system Architecture and system configuration controller for WIZnet W7500 system part.

We will also learn about WIZnet W7500 memory organization and memory map for WIZnet W7500 memory part.

System Architecture

Main system consists of:

  • Two masters:
    • Cortex-M0 core
    • uDMAC(PL230, 60channel)
  • Ten slaves
    • Internal BOOT ROM
    • Internal SRAM
    • Internal Flash Memory
    • Two AHB2APB bridge which connects all APB peripherals
    • Four AHB dedicated to 16-bit GPIOs
    • TCPIP Hardware core

pic 1

AHB-Lite BUS – This bus connects the two masters (Cortex-M0 and uDMAC) and ten AHB slaves. Two APB BUSs – These buses connect Seventeen APB peripherals (Watchdog, two dual timers, pwm, two UARTs, simple UART, two I2Cs, two SSPs, random number generator, real time clock, 12bits analog digital converter, clock controller, IO configuration, PAD MUX controller)

Memory Organization

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.

Memory Map

pic 2

System Configuration Controller (SYSCFG)

Main purposes of the system configuration controller are the following

  • Control of the memory remap feature
  • The ability to enable an automatic reset if the system locks up
  • Information about the cause of the last reset

If you have any question and inquiry about this product, please contact our support team at support_team@wiznettechnology.com.